The present invention relates to a semiconductor integrated circuit in which memories are integrated. Particularly, it relates to a semiconductor integrated circuit in which a logic circuit such as a CPU (central processing unit) is integrated with a large-capacity memory in one chip. For example, it relates to a useful technique adapted for embedded DRAM which is integrated with a CPU and a first level cache memory in one and the same chip.
Today, a semiconductor integrated circuit in which a large-scale logic circuit is integrated with a large-capacity memory in one chip is provided. In such a semiconductor integrated circuit, the number of bus bits for connecting the memory and the logic circuit to each other can be increased easily, for example, to 128 in order to enhance data throughput between the memory and the logic circuit. Accordingly, there is an advantage in that data can be transferred at a high speed while electric power consumption required for data input/output is suppressed compared with the case where input/output pins outside the chip are driven.
Multi-bank DRAM (Dynamic Random Access Memory) can be used as the large-capacity memory. In the multi-bank DRAM, a sense amplifier is provided in accordance with every memory bank, so that data once latched by the sense amplifier on the basis of a word line selecting operation can be output successively at a high speed by a simple means for changing-over a column switch. Accordingly, data access to continuous addresses in one and the same page (one and the same word line address) can be made relatively speedily. Data access to different pages (at page-miss) is, however, made slow because of bit line precharge, or the like.
Further, in the multi-bank DRAM, page-miss can be hidden under a predetermined condition. That is, when a read or write command is generated to operate a certain memory bank and another memory bank is to be used next, an activation command can be given to the next memory bank in advance to make a word line selecting operation precedently. Of course, for this reason, the CPU must make access to the addresses sequentially. It is, however, substantially impossible to define this entirely by a CPU operation program, or the like.
In semiconductor integrated circuits, there is also that in which a cache memory integrated with a large-capacity memory and a large-scale logic circuit such as a CPU, or the like. In the semiconductor integrated circuit of this type, the difference in operating speed between the large-capacity memory and the CPU is relaxed by the cache memory so that data can be processed at a high speed by the CPU. That is, among data stored in the large-capacity memory, a part of data used recently by the CPU and data in its vicinity are held in the high-speed cache memory. The data processing speed is enhanced when the memory access of the CPU is hit to the cache memory. However, when a miss occurs once, access to the large-capacity memory is made. As a result, data processing speed of the CPU is limited.
An example of literature on the multi-bank DRAM is JP-A-10-65124 corresponding to U.S. patent application Ser. No. 08/813900 filed Mar. 7, 1997 and U.S. patent application Ser. No. 09/188367 filed Nov. 10, 1998, a continuation application of application Ser. No. 08/813900, the whole disclosure of which is incorporated herein by reference.
As described above, even in the multi-bank DRAM, page-miss is not always hidden in accordance with a sequence of access addresses. Even in the case where a cache memory is provided for the multi-bank DRAM, the situation is quite the same if cache-miss occurs. Therefore, the necessity of improving the access speed to the multi-bank memory more greatly has been found by the inventor.
A first object of the present invention is to enhance the speed of first access to a multi-bank memory, that is, the speed of read access different in word line from the previous access.
A second object of the present invention is to prevent lowering of the operating efficiency of a multi-bank memory having a plurality of banks which are able to operate parallelly when both cache entry replace and write back are caused by cache-miss of a cache memory provided for the multi-bank memory. That is, address information corresponding to an index address in an address signal is made identical between an operation in which data in a cache line to be written back are written in a multi-bank memory and an operation in which new cache entry data to be written in the same cache line as described above are read from the multi-bank memory. When information of the index address is mapped in memory bank selection address information, data having the index addresses arranged as one and the same address are arranged in one and the same memory bank. Accordingly, both a read operation for replacing the cache line with new one and a write operation for write back must be performed on one and the same memory bank. Accordingly, the two operations cannot be performed efficiently by use of different memory banks.
A third object of the present invention is to make non-blocking multi-access possible in a semiconductor integrated circuit having a plurality of multi-bank memory macro structures in which a plurality of access requests without conflict among the memory macro structures are allowed so that one access does not block another access.
A fourth object of the present invention is to enhance the efficiency of data rewrite to a multi-bank DRAM having a cache line with every word line. That is, the inventor has found that, when the cache line is provided as a rewrite unit, there is no necessity of performing read modify write to apply write data after storage information read out to a bit line by a word line selecting operation is latched by a sense amplifier, in the same manner as in a general DRAM.
The foregoing and other objects and novel features of the present invention will become clear from the following description and the accompanying drawings.
Main features in embodiments of the present invention contain the following features.
 less than 1 greater than  Next Address Self-prefetching
A multi-bank memory macro structure is used and data are held in a sense amplifier in every memory bank. When access is hit to the data held in the sense amplifier, data latched by the sense amplifier are output so that the speed of first access to the memory macro structure can be made high. That is, every memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of the sense amplifier cache (the ratio of hit on the data of the sense amplifier) more greatly, after access to one memory bank, the next address (obtained by addition of a predetermined offset) is self-prefetched so that data in the self-prefetching address is preread by a sense amplifier in another memory bank. The next address is used as a subject of self-prefetching on the basis of an empirical rule that CPU operation programs or a group of processing data are basically mapped on linear addresses.
A semiconductor integrated circuit for achieving the aforementioned next address self-prefetching comprises memory macro structures 5Ma to 5Md, and an access controller 4. Each of the memory macro structures has a plurality of memory banks BANK1 to BANK4 having bank addresses allocated thereto respectively. Each of the memory banks has a sense amplifier 53 for latching storage information read out to a bit line BL from a memory cell in a word line WL selected on the basis of a row address signal R-ADD. The bit line is selected on the basis of a column address signal Ys0 to Ys7. The selected bit line is connected to a data line GBL of the memory macro structure. The access controller includes an address/command generating unit 44 for generating the address/command and being able to operate for every memory bank, a hit/miss judgment unit 43 for enabling data already latched by the sense amplifier to be output to the data line in response to an access request after the data latching, and an address self-prefetching unit 42 for self-prefetching an access address having a predetermined offset to an external access address after access control of the memory macro structure to the external access address so that data in the self-prefetching address is preread from a corresponding memory cell of the memory macro structure.
The self-prefetching address must be an address in a memory bank different from a subject of access just before the self-prefetching address. If the two addresses are in one and the same memory bank, the function of a sense amplifier cache cannot be used for the preceding access. For this reason, the access address having a predetermined offset to the external access address is provided as an address for designating a memory bank different from the memory bank designated by the external access address. From a different point of view, the address signal generated by the address/command generating unit is formed so that a bank address signal B0 to B3 is mapped on the high order side of a column address signal C0 to C2, a row address signal R0 to R7 is mapped on the high order side of the bank address signal, and the predetermined offset is 2 to the power i from the least significant bit of the column address signal when i is the number of bits in the column address signal.
The hit/miss judgment unit for the sense amplifier cache function can be formed so as to have comparators 432A and 432B for detecting coincidence/anticoincidence between the external access address and the storage information access address held in the sense amplifier. The address/command generating unit can be formed so as to give an instruction to the memory macro structure designated by the external access address to select the memory bank, the word line and the bit line in response to anticoincidence detected by the comparator and give an instruction to the memory macro structure designated by the external access address to stop the word line selecting operation and select the memory bank and the bit line in response to coincidence detected by the comparator.
 less than 2 greater than  Address Alignment Control for Second Level Cache
When the CPU 1 is connected to the access controller 4 and a set associative type first level cache memory 2 is connected both to the CPU and to the access controller, the access controller and the memory macro structures can be provided as a second level cache memory 6 based on the sense amplifier cache function thereof. Those as a whole may be configured as a multi-chip data processing system. There is some case where both replace of the cache line concerning cache-miss with new one and write back of the cache line are required because of cache-miss of the first level cache memory. In this case, index addresses for the first level cache memory are made identical to each other between an operation in which data in the cache line concerning the cache-miss of the first level cache memory are written back to the second level cache memory and an operation in which cache entry data to be substituted for the cache line concerning the cache-miss are read from the second level cache memory. If memory bank address information for the second level cache memory is the same as index address information for the first level cache memory, data in index addresses identical to each other are arranged in one and the same memory bank on the second level cache memory. Accordingly, both a read operation for replacing the cache line with new one and a write operation for write back must be performed for one and the same memory bank. Accordingly, the two operations cannot be performed efficiently by use of different memory banks.
Therefore, an address alignment control unit 41 is provided in the access controller for changing the bit alignment of an access address signal supplied from the outside to output the changed bit alignment to the memory macro structure. For example, the address alignment control unit is provided to allocate the alignment of an address signal supplied from the CPU and different from the alignment of a plurality of address bits allocated to the index address of the first level cache memory to the bank address of the memory bank. As a result, cache entry replacement caused by cache-miss of the first level cache memory can be performed without lowering of the operating efficiency of the multi-bank memory.
From another point of view, the address alignment control unit is provided to change at least the whole or a part of the alignment of address information contained in an address signal provided from the CPU, which is used as the index address of the first level cache memory to allocate the changed alignment to the bank address of the memory bank. For example, the address alignment control unit is provided so that a part of address information contained in an address signal supplied from the CPU and used as an index address of the first level cache memory and a part of address information used as a tag address are replaced with each other to allocate the address information to the bank address of the memory bank.
As another example of address alignment by the address alignment control unit, at least low order 2 bits of the tag address of the first level cache memory contained in the address signal supplied from the CPU can be allocated to an address for designating the memory bank and/or an address for designating the memory macro structure. Alternatively, at least low order 2 bits of the index address of the first level cache memory contained in the address signal supplied from the CPU can be allocated to an address for designating the memory bank and/or an address for designating the memory macro structure. Further, at least low order 2 bits of the index address of the first level cache memory contained in the address signal supplied from the CPU can be allocated to the column address signal.
The address alignment control unit may contain a switch circuit 411 for making the alignment change of address information variable, and a control register 410 for latching control information for determining the switch state of the switch circuit. Access to the control register can be performed by the CPU. The difference in address alignment appears as the difference in frequency of designation of one and the same memory bank with respect to continuous addresses. If the frequency of selection of one and the same memory bank with respect to index addresses close to each other is high at the time of cache line replacing, the hit ratio of information due to the sense amplifier cache function becomes lower as access address are closer to each other. If the frequency of selection of different memory banks with respect to index addresses close to each other is high at the time of cache line replacing, the hit ratio of information due to the sense amplifier cache function becomes higher as access address are closer to each other. Which is selected advantageously depends on the address mapping of data/command. One of the two can be selected in accordance with an application system.
If the simplification of configuration is put first, wiring having address alignment fixed by a metal option can be used as the address alignment control unit.
 less than 3 greater than  Write without Data Readout in Second Level Cache Memory constituted by DRAM Macro Structures
For writing data in DRAM, generally, data is once read from a memory cell to a sense amplifier and then a part of data is rewritten. That is, read modify write is performed. When the sense amplifier cache function of the DRAM macro structures is used as a second level cache memory, there is no necessity of performing read modify write because data are managed by word lines. Therefore, for writing, transfer of write data from a write amplifier to a bit line is started at the same time or just after rising of a word line without the read operation of the sense amplifier, so that one-word-line""s data are written at a high speed.
The cache memory for achieving the aforementioned write without data readout comprises DRAM macro structures 5Ma to 5Md, and an access controller 4. Each of the DRAM macro structures has a plurality of memory banks BANK1 to BANK4 having bank addresses allocated thereto respectively. Each of the memory banks has a sense amplifier 53 for latching storage information read out to a bit line from a memory cell in a word line WL selected on the basis of a row address signal R-ADD. The bit line BL is selected on the basis of a column address signal C-ADD. The selected bit line is connected to a data line GBL of the corresponding DRAM macro structure. The access controller includes an address/command generating unit 44 for generating the address/command and being able to operate for every memory bank, and a hit/miss judgment unit 43 for making it possible to output data already latched by the sense amplifier to the data line in response to an access request after the data latching. Each of the memory banks has a first operation mode for activating the sense amplifier at first timing after selection of the word line, and a second operation mode for activating the sense amplifier at second timing slower than the first timing after selection of the word line. The first operation mode is a write without data readout mode. The second operation mode is a refresh mode. A data processing system can be configured by using the aforementioned cache memory as a second level cache memory and by using a first level cache memory and a CPU for the second level cache memory.
 less than 4 greater than  Parallel Access to Non-conflicting Memory Macro Structures
In a semiconductor integrated circuit in which a plurality of multi-bank memory macro structures are integrated, non-blocking multi-access can be provided for a plurality of access requests without conflict among memory macro structures so that one access does not block another access. The memory 6 for achieving this access comprises an access controller 4 having a first access port PT1 and a second access port PT2, and a plurality of memory macro structures 5Ma to 5Md connected to the access controller through data lines 9DBa to 9DBd respectively. Each of the memory macro structures has a plurality of memory banks BANK1 to BANK4 having bank addresses allocated thereto respectively. Each of the memory banks has a sense amplifier 53 for latching storage information read out to a bit line BL from a memory cell in a word line WL selected on the basis of a row address signal R-ADD. The bit line is selected on the basis of a column address signal C-ADD. The selected bit line is connected to a data line GBL of the memory macro structure. The access controller includes selectors 450R, 451R, 452W and 453W for selecting a memory macro structure accessed through the first access port and a memory macro structure accessed through the second access port, an access priority judgment unit 40 permitting parallel access through the two access ports when both the access through the first access port and access through the second access port use different memory macro structures respectively, an address/command generating unit 44 for generating the address/command and being able to operate for every memory bank in the memory macro structure to be accessed, and a hit/miss judgment unit 43 for making it possible to output data latched by the sense amplifier to the data line in response to an access request after the data latching.
For conflicting memory macro priority control, the access priority judgment unit can be formed so that the operation of an access port having higher priority determined in advance is performed preferentially when both the access through the first access port and access through the second access port use one and the same memory macro structure.
Further, the first access port and/or second access port can have an SRAM interface function. Latency from address input to data output changes in accordance with the state of access. To cope with this, an SRAM interface which is able to output a wait signal, or the like, in a period from address input to data output is used in the first and second access ports more simply than an interface having fixed latency.
A data processing system using the memory 6 comprises the memory 6, a combination of a first address bus 6AB and a first data bus 10DB connected to the first access port of the memory, a combination of a second address bus 11AB and a second data bus 11DB connected to the second access port of the memory, a CPU 1 connected both to the first address bus and to the first data bus, and a bus interface circuit 3 connected both to the second address bus and to the second data bus.
Alternatively, a data processing system using the memory comprises the memory 6, a combination of a first address bus 6AB and a first data bus 10DB connected to the first access port of the memory, a combination of a second address bus 11AB and second data bus 11DB connected to the second access port of the memory, a combination of a CPU 1 and a first level cache memory 2 connected both to the first address bus and to the first data bus, and a bus master 7 connected both to the second address bus and to the second data bus, wherein the memory is used as a second level cache memory for the first level cache memory.